In integrated circuits (ICs), various devices such as transistors, resistors, inductors, capacitors and varactors are configured to achieve the desired function. These devices are electrically isolated to ensure that they operate independently without interfering with each other. This can be achieved by forming isolation regions to prevent carriers from moving between neighboring semiconductor components.
To electrically isolate devices on the substrate, shallow trench isolations (STIs) are typically employed. STIs are formed by etching trenches in the substrate and filling them with a dielectric material. To facilitate filling high aspect ratio trenches, tapered or slanted sidewalls are used. The smaller the angle of the tapered sidewalls (or the more slanted the sidewalls), the easier it is to fill the trench. With current ground rules (GRs) and depth requirements, etching trenches with a desired angle Q results in a merged or pinched bottom surface 108, as shown in FIG. 1a. 
As indicated by FIG. 1b, a trench having a width of 70 nm and a depth of 280 nm would merge at a tapered angle of less than 84°. In order to have a bottom surface, the angle needs to be greater than 84°. For example, the bottom surface would be 15 nm wide for Q of 84.5°, 30 nm wide for Q of 86° and 45 nm wide for Q of 87.5°. Furthermore, with Q of less than 84°, the depth of the trench decreases due to pinching of the sidewalls at shallower depths. The bottom surface of the STIs is where the n-well and p-well implant intersect. Pinching the bottom surface leaves little margin for overlay, limits the angle that can be achieved for a given depth or limits the trench depth. These issues can result in current leakage issues which degrade performance and/or reliability.
From the foregoing discussion, it is desirable to provide STIs with a tapered profile and flatter bottom.